1. Field of the Invention
The present invention generally relates to a DC test circuit and a test method of a semiconductor device and particularly relates to a semiconductor device and a test method that implement test by short-circuiting a plurality of LSI signal terminals to make a connection with an LSI tester.
2. Description of Related Art
The number of LSI signal terminals is on the increase recently. On the other hand, the number of tester terminals of an LSI tester does not keep up with the ever increasing signal terminals. Particularly, an LSI tester is highly expensive, and use of a multiple pin LSI tester directly affects product test costs, which is thus not easy. Consequently, various techniques to enable testing by assigning a small number of tester terminals to a larger number of LSI signal terminals have been investigated.
Normally, an LSI signal terminal (which is referred to hereinafter as the “external terminal”) and an LSI tester terminal (hereinafter as the “tester terminal”) are connected one to one to test an LSI. On the other hand, there is proposed a technique that short-circuits (hereinafter as “integrates”) a plurality of external terminals outside the LSI by jig tool and connects the integrated terminals to one tester terminal. This technique then activates one test target external terminal by turning an enable (EN) value of input/output mode to ON and thereby tests the terminals one by one. This technique is described in Japanese Patent No. 3072718 and Japanese Unexamined Patent Application Publication No. 2003-337157, for example.
The ON/OFF value of EN is arbitrary for each LSI or interface (I/F) buffer. In this specification, ON (output mode) of the EN value is “1” and OFF (input mode) is “0”.
FIG. 17 is a circuit diagram that shows the entire part of a boundary scan (BSCAN) circuit of a related art. As shown in FIG. 17, the LSI of the related art includes an internal logic circuit 102 for implementing desired functions and data input/output (I/O) circuits 111a, 111b and 111c, formed on an LSI substrate 101. The data I/O circuit 111a includes a bidirectional buffer 200 that transmits a logic signal with the outside of LSI, and a BSCAN circuit 210. The BSCAN circuit 210 includes a data side BSCAN register 115a, a data side Update latch 116a, an EN side BSCAN register 115b, an EN side Update latch 116b, selectors 114a to 114c, and an AND gate (AND circuit) 118.
An LSI external terminal IO1 that is connected to a bidirectional terminal A of the bidirectional buffer 200 is short-circuited (integrated) with another external terminals IO2 and IO3 by an LSI tester (not shown) outside the LSI or a jig 220 for connecting the LSI substrate 101 and the tester terminal.
The bidirectional buffer 200 and the BSCAN circuit 210 are connected as follows. A data input terminal B of the bidirectional buffer 200 is connected to the output of a selector 114a, an EN input terminal C of the bidirectional buffer 200 is connected to the output of a selector 114b, and a data output terminal D of the bidirectional buffer 200 is connected to the input NO2 of the internal logic circuit 102. The input NO2 is also connected to a selection input with a switching input value “0” of a selector 114c. 
One input (logical inversion input) of the AND circuit 118 receives a BSCAN control signal MODE1 from a test access port (TAP) circuit 110, the other input is connected to the output of the selector 114b, and the output is connected to a switching input of the selector 114c. In the selector 114c, the selection input with the switching input value “0” is connected to the output HO1 of the internal logic circuit 102, and the selection input with the switching input value “1” is connected to the output of the data side Update latch 116a. The switching input of the selector 114a receives a BSCAN control signal MODE1 from the TAP circuit 110, and the output of the selector 114a is connected to the data input terminal B of the bidirectional buffer 200 and the selection input with the switching input value “1” of the selector 114c. 
In the selector 114b, the selection input with the switching input value “0” is connected to the output HO3 of the internal logic circuit 102, and the selection input with the switching input value “1” is connected to the output of the EN side Update latch 116b, the switching input receives a BSCAN control signal MODE1 from the TAP circuit 110, and the output is connected to the EN input terminal C of the bidirectional buffer 200.
In the selector 114c, the selection input with the switching input value “0” is connected to the data output terminal D of the bidirectional buffer 200, the selection input with the switching input value “1” is connected to the output of the selector 114a. Further, the switching input of the selector 114c is connected to the output of the AND circuit 18, and the output of the selector 114c is connected to the PIN input of the data side BSCAN register 115a. 
A PIN input of the data side BSCAN register 115a is connected to the output of the selector 114c, a SFDR input thereof receives a BSCAN control signal SFDR from the TAP circuit 110, a CLKDR input thereof receives a BSCAN control signal CLKDR from the TAP circuit 110, and a POUT output thereof is connected to the data input of the data side Update latch 116a. Further, a BSIN input of the data side BSCAN register 115a is connected to a BSOUT of the EN side BSCAN register 115b, and a BSOUT output thereof is connected to BS_SIN of the TAP circuit 10.
A PIN input of the EN side BSCAN register 115b is connected to the output H03 of the internal logic circuit 102, a SFDR input thereof receives a BSCAN control signal SFDR from the TAP circuit 110, a clock input (GB=CLKDR) thereof receives a BSCAN control signal CLKDR from the TAP circuit 110, and a POUT output thereof is connected to the data input of the EN side Update latch 116b. Further, a BSIN input of the EN side BSCAN register 115b is connected to a BSOUT of the data I/O circuit 111b, and a BSOUT output thereof is connected to a BSIN input of the data side BSCAN register 115a. 
The data input of the data side Update latch 116a is connected to the POUT output of the data side BSCAN register 115a, the clock input (G=UPDDR) thereof is connected to UPDDR of the TAP circuit 110, and the output thereof is connected to the selection input with the switching input value “1” of the selector 114a. 
The data input of the EN side Update latch 116b is connected to the POUT output of the EN side BSCAN register 115b, the clock input (G=UPDDR) thereof is connected to UPDDR of the TAP circuit 110, and the output thereof is connected to the selection input with the switching input value “1” of the selector 114b. 
The data I/O circuits 111b and 111c each have the similar circuits such as the data side and the EN side BSCAN registers. The BSOUT output of the data side BSCAN register (not shown) of the data I/O circuit 111b is connected to the BSIN input of the EN side BSCAN register 115b of the data I/O circuit 111a. The BSIN input of the EN side BSCAN register (not shown) of the data I/O circuit 111b is connected to the BSOUT output of the data side BSCAN register (not shown) of the data I/O circuit 111c. 
The BSOUT output of the data side BSCAN register (not shown) of the data I/O circuit 111c is connected to the BSIN input of the EN side BSCAN register (not shown) of the data I/O circuit 111b. The BSIN input of the EN side BSCAN register (not shown) of the data I/O circuit 111c is connected to BS_SOUT of the TAP circuit 110. The other elements in the data I/O circuits 111b and 111c are connected in the same manner as those in the data I/O circuit 111a. 
Test operation of a related art is described herein. FIG. 18 is a flowchart showing test operation according to a related art. FIG. 19 is a flowchart showing a detail of Step S105 in FIG. 18. FIGS. 20 and 21 are views to describe the test operation of a related art. The circuit shown in FIG. 20 includes a three-state (3st) output buffer 203 having three states of “1”, “0” and “High-Z (high impedance)”, instead of the bidirectional buffer 200 of the data input circuit 111a of FIG. 17. This circuit omits the AND circuit 118 of the BSCAN circuit 210, the control signals SFDR, CLKDR, UPDDR and MODE1 of the TAP circuit 110, and the TAP circuit 110. Referring to FIGS. 20 and 21, in the data input circuits 111a, 111b and 111c, “X” in the input and the EN side BSCAN registers indicates the value of “1” or “0”, and “1” or “0” in each Update latch indicates the value which is held during DC test. The BSCAN operation, including the state transition in the TAP circuit 110 (=mode change), is defined by IEEE1149.1 and well known to those skilled in the art, and therefore the detail of the operation is not described herein.
Referring first to FIG. 18, the process integrates (short-circuits) external terminals IO1 to IO3, which are LSI test target terminals, by a jig tool 220 (S101 in FIG. 18) and turns on power (S102 in FIG. 18). In the following description, the external terminals to be integrated are referred to herein as the “integration terminal group”, and the number of integrated external terminals is N. The process then sets BSCAN to Extest mode (S103), controls EN values sequentially and performs DC test of the 3st buffer 203 of the data input circuit 111a and the bidirectional buffers 200 of the data input circuits 111b and 111c (S104 and S105). Further, the process detects errors in the internal logic circuit 102 by a functional test pattern such as a scan path (hereinafter as SCAN) while controlling the EN values, thereby performing error detection (operational test) of the circuits including the input/output/bidirectional buffers by BSCAN (S106).
The BSCAN in S103 uses Extest mode. The Extest mode disconnects the transmission of the output of the LSI internal logic circuit 102 to the bidirectional buffers at the selectors 114a and 114b. Then, the value of the BSCAN register 115a which are sequentially shift-input (ShI/Ft_DR) through the BSCAN data input terminal TDI is read into the Update latch 116a and output to the bidirectional buffer 200 (Update_DR), or the values input to the bidirectional buffer 200 is captured (Capture_DR) through the selector 114c to the EN side BSCAN resistor 115b and sequentially shift-output (ShI/Ft_DR) to the terminal TDO. The BSCAN data input terminal TDI is a terminal for inputting a set value from the outside of the LSI to the BSCAN register. The terminal TDO is a terminal for outputting the value of the EN side BSCAN register 115b to the outside of the LSI.
FIG. 22 is a view showing a detail of the BSCAN circuit of the bidirectional buffer 200. In this case, the value of MODE1 supplied from the TAP circuit is fixed to “1” during Extest mode while it is fixed to “0” in other times.
The DC test implemented by the 3st output buffer and the bidirectional buffer 200 in Step S105 of FIG. 18 is described hereinafter in detail. As shown in FIG. 19, the process determines whether to initialize the setting or not (S111). “n” indicates any of the N number of external terminals which are included in the integration target terminal group. When performing initialization, the process sets n=0 and proceeds to Step S112. The value of “n” is 0, 1, . . . , N and the termination condition, which is described later, is n=N.
Then, “0” is shift-input to the EN side BSCAN register 115b through the BSCAN data input terminal TDI so as to set the EN value of all the selectors 114a to OFF (S112), and further “0” is shift-input to the data side BSCAN register 115a through the BSCAN data input terminal TDI. After setting “0” to the BSCAN registers 115a and 115b, the values of the BSCAN registers 115a and 115b are read into the Update latches 116a and 116b. Then, TAP mode is changed from Shift_DR, then Exite_DR to Update_DR, and thereby set to Update_DR (S114). After that, the values of the BSCAN registers 115a and 115b are read into the Update latches 116a and 116b (S115).
Then, TAP mode is changed from Update_DR, then Select_DR_scan, Capture_DR to Shift_DR, and thereby set to Shift_DR (S117). Consequently, the EN values of all of the 3st output buffer 203 and the bidirectional buffer 200 are set to OFF.
Then, DC test is implemented under the state where the EN values of all the 3st output buffer 203 and the bidirectional buffer 200 are OFF (S117). After the test, if the number n of current test target external terminals does not reach the number N of integration terminals or if the termination condition is not satisfied (NO in S118), the process increments the value of n and designates the next test target terminal (buffer) (S119). Then, the process sequentially inputs a value through the BSCAN data input terminal TDI so that the EN value of the test target buffer 200 only is set to ON and thereby sets a set value “1” to the BSCAN register 115a (S113). A series of operation from S112 to S116 is the operation of Extest mode of BSCAN, which sets DC test conditions to the 3st output buffer and the bidirectional buffer and implements DC test. This process is repeated until the DC test on all of the 3st output buffer 203 and the bidirectional buffer 200 is completed.
However, the above-described technique has the following problems. First, the short-circuit which occurs between the external terminals of different integration terminal groups can be detected just like the case where an external terminal and a tester terminal are connected one to one. However, if the short-circuit occurs between the terminals of the same integration terminal group as shown in FIG. 20, this error is undetectable in principle. Because the short-circuit path is configured outside the LSI by design using the integration jig tool 220, the short-circuit error and the short-circuit for integration cannot be distinguished, thus failing to detect the short-circuit error.
In a conventional test method where an external terminal and a tester terminal are connected one to one, one technique of test for detecting a short-circuit error is to perform short-circuit detection by setting different conditions for test target terminals and for other terminals. For example, after setting VDD=GND, this technique supplies a signal of 0.1V to the terminals other than a test target terminal and detects the occurrence of short-circuit (path) based on observation of current at the test target terminal. However, if external terminals are integrated as in the above-described test method, it is unable to set different conditions for different terminals and an integrated path (short-circuit path) exists outside the LSI, and therefore it is impossible to detect the occurrence of short-circuit error in the same integration group by test.
A second problem is as follows. When a plurality of degeneracy errors where a logic is fixed to “1” or “0” occur in the same integration target terminal group or when multiple errors occur in the integration terminal group as shown in FIG. 21, if at least one of the errors causes logic fixation to “1” (formation of a path reaching VDD) and at least one causes logic fixation to “0” (formation of a path reaching GND), VDD−GND short-circuit occurs by the integration jig tool 220 upon application of power and connection of the integration jig tool 220, which causes excessive current flow.
If an external terminal and a tester terminal are connected one to one as in the conventional test method, the above-described current path is not formed even if the 3st output buffer with a high driving force or the bidirectional buffer contains an error. However, if the terminals are integrated outside the LSI by the jig tool 220 as in the above-described test method, the above current path is formed due to multiple errors. Excessive current thereby flows through the current path, which can cause breakdown of a jig tool such as a probe card.
A third problem is as follows. Though a condition for stable implementation of test is to set only one terminal at most in each integration target terminal group to output mode, it is unable to satisfy this condition after power-on until the completion of EN value setting by BSCAN operation, which causes VDD−GND short-circuit to occur.
As shown in FIGS. 18 and 19, in order to set the EN values of the 3st output buffer 203 and the bidirectional buffer 200 by BSCAN operation after integrating the external terminals outside the LSI by a jig in S101 and turning on the power in S102, the following series of process is required. First, the mode is set to Extest mode in S103 after resetting the BSCAN circuit. Then, in S112, a desired EN value is sequentially shifted to the BSCAN register through the BSCAN data input terminal TDI. Further, after completing the shift, Update_DR operation is performed in S114, and the EN value is set.
The operation for setting to Extest mode after resetting the BSCAN circuit (S103) requires several patterns (clocks). Further, the sequential shifting of a desired EN value to the BSCAN register through the BSCAN data input terminal TDI (S112) requires at least the same number of patterns (clocks) as the number of BSCAN registers. Thus, even the configuration of FIG. 17 that uses two BSCAN registers (BSCAN registers 115a and 115b) for the bidirectional buffer requires 1000 patterns (clocks) if there are 500 bidirectional terminals, for example. As a result, a time to set the EN value is not a temporary short time immediately after power-on but takes a long time.
As described in the foregoing, the present invention has recognized that when it is impossible to detect whether an EN value is settled at “0” or “1” upon power-on until completion of EN value setting and when integration target terminals with the output buffers such as the bidirectional buffer 200 and the 3st output buffer 203 are integrated, if one outputs “1” while the other outputs “0”, a path of VDD−GND short-circuit is formed to cause breakdown of a jig tool such as a probe card as in the second problem.